1. Field of the Invention
The present invention relates to a process for fabricating doped polycrystalline silicon and/or polycrystalline silicide gate integrated CMOS devices, and more particularly to a process for fabricating devices having a sub-micron gate length designed to operate with a relatively high supply voltage.
2. Description of the Prior Art
According to state-of-the-art fabrication technology of CMOS devices, e.g. n-welltype devices, wherein polycrystalline silicon and/or polycrystalline silicide gate structures are commonly subjected to n-type doping on n-channel transistors as well as on p-channel transistors in order to obtain an acceptable threshold voltage, the practice of introducing, in these integrated circuits, "buried" p-channel transistors is common. These special transistors are obtained during the fabrication process of the device by creating a thin p-doped region at the surface of n-well regions; i.e. above the channel region of a p-channel transistor. This configuration, if from one side allows appropriate adjustment of the threshold voltage value, determines far from optimal electrical characteristics especially for transistors having a very small gate length, such as a relatively steep "below ground" curve and an increased sensitivity to punch-through. Moreover, the thickness of this p-doped region below the gate of the transistor constitutes a very critical feature because a too thick layer would cause the device to operate as a depletion type MOS transistor with totally different and inadequate characteristics. Of course, with correctly inverted polarities, the same problem also arises in p-well CMOS devices as well as in twin-well devices.